The use of configurable integrated circuits (“IC's”) has dramatically increased in recent years. One example of a configurable IC is a field programmable gate array (“FPGA”). An FPGA is a field programmable IC that often has logic circuits, interconnect circuits, and input/output (I/O) circuits. The logic circuits (also called logic blocks) are typically arranged as an internal array of circuits. The logic functions of these circuits are typically configured by the contents of an internal Static Random Access Memory (SRAM) which is loaded with data from an external source prior to operation.
FIG. 1 illustrates an example of a configurable logic circuit 100. This logic circuit can be configured to perform a number of different functions. As shown in FIG. 1, the logic circuit 100 receives a set of input data 105 and a set of configuration data 110. The configuration data set is stored in a set of SRAM cells 115. From the set of functions that the logic circuit 100 can perform, the configuration data set specifies a particular function that this circuit has to perform on the input data set. Once the logic circuit performs its function on the input data set, it provides the output of this function on a set of output lines 120. The logic circuit 100 is said to be configurable, as the configuration data set “configures” the logic circuit to perform a particular function, and this configuration data set can be modified by writing new data in the SRAM cells. Look-up tables are examples of configurable logic circuits.
FIG. 2 illustrates an example of a configurable interconnect circuit 200. This interconnect circuit 200 connects a set of input data 205 to a set of output data 210. This circuit receives configuration data bits 215 that are stored in a set of SRAM cells 220. The configuration bits specify how the interconnect circuit should connect the input data set to the output data set. The interconnect circuit 200 is said to be configurable, as the configuration data set “configures” the interconnect circuit to use a particular connection scheme that connects the input data set to the output data set in a desired manner. Moreover, this configuration data set can be modified by writing new data in the SRAM cells. Multiplexers are one example of interconnect circuits.
During operation, the contents of SRAM 220 are susceptible to random bit errors (soft errors) due to high-energy atomic particles (such as alpha particles or neutrons) traveling through the chip releasing an avalanche of electrons. The electrons find their way either to the positive supply or to an SRAM storage cell representing one bit of memory. If the total electrical charge reaching the storage cell is larger than the critical charge to upset logic, a soft error takes place. As semiconductor geometries and voltage levels are reduced in order to provide more functionality per chip, the critical charge level is reduced, making soft errors more likely. Undetected, such errors can seriously effect the logical operation of the FPGA and thus affect the system in which it is used, often in unpredictable ways.
One prior art solution to this problem involves a process called scrubbing, which periodically reads back the contents of the configuration memory to an external system, and compares the read-back data to the original data. If a discrepancy is detected, the subsystem using the FPGA can be stopped, the FPGA configuration memory downloaded again and then operation continued. One problem with this approach is that it takes time away from the external process which could have been used to execute other tasks. A second problem with this approach is that it results in a high probability that a system fault will occur between the times the external system checks the configuration memory.
Another prior art solution to the problem involves the application of triple modular redundancy (TMR). With TMR, the IC requires three copies of the user circuit, all of which are initially loaded with the same data by a configuration network. During operation, the outputs of the three circuits are compared to each other. If one of these differs from the other two, then only data from one of the two matching circuits is used. The primary problem with this method is that it requires more than three times as much IC real estate to implement.
Accordingly, there is a need for a configurable IC that has the ability to check and correct its configuration memory continuously, during normal operation of the system in which it is embedded. Moreover, there is also a need for a configurable IC that has the ability to check and correct its configuration memory independently of the external system.